The present invention relates to nonvolatile semiconductor memory devices including MOS transistors.
Among nonvolatile semiconductor memory devices, flash memories, e.g., are frequently used as devices capable of retaining large amounts of data in a nonvolatile manner.
In flash memories, flash cells, each having a single transistor structure typically formed by stacking a control gate on a floating gate, are used. Along with finer design rules, however, fabrication process steps of flash memories have become more complicated and their processing cost has been increasing. In view of this, in the case of incorporating nonvolatile memories into a large-scale system LSI, it is required to use low-cost nonvolatile semiconductor memory devices in which typical MOS transistors are used, instead of transistors having such a high-cost stacked structure.
FIG. 7 illustrates an exemplary structure of a conventional nonvolatile semiconductor memory device in which MOS transistors are used (see Japanese Laid-Open Publication No. 2001-229690).
As shown in FIG. 7, a bit cell 100 includes a PMOS transistor 101 and a first NMOS transistor 103. The source, drain and substrate of the PMOS transistor 101 are electrically connected to form a control gate. The source of the first NMOS transistor 103 is connected to a source line SL, while the gate thereof is used in common with the PMOS transistor 101 and forms a floating gate 102.
The drain of the first NMOS transistor 103 is connected to the source of a second NMOS transistor 104, and the drain of the second NMOS transistor 104 is connected to an input node bit of a pair of serially connected inverters 105 for driving an output signal.
The input node bit is connected to a shared drain (output node) of a load transistor 106 formed of a PMOS transistor and a switch transistor 107 formed of a third NMOS transistor.
Hereinafter, it will be described how the conventional nonvolatile semiconductor memory device with the above-mentioned structure operates.
First, to write desired data into the bit cell 100, a high-level write control signal prog is applied to the gate of the switch transistor 107 in order to turn ON the switch transistor 107. Furthermore, a control gate control signal cg of 5 V, which is a relatively high voltage, is applied to the PMOS transistor (control gate) 101, and a high voltage of 5 V is also applied to the source line SL. As a result, a channel is formed in the first NMOS transistor 103 to allow the first NMOS transistor 103 to turn on. At this time, channel hot electrons are generated in the channel and part of the electrons passes through the gate oxide film of the first NMOS transistor 103 to be injected into the floating gate 102. Whether or not the charge is injected into the floating gate 102 corresponds to 1-bit data.
Next, to read the written data from the bit cell 100, a control gate control signal cg of 1 V is applied to the control gate 101, and a read permission signal tg of 1 V is applied to the second NMOS transistor. At the same time, the source line SL is put to 0 V and a read control signal /read is put to a low level (0 V) so that the load transistor 106 is turned ON so as to pass current through the source line SL.
If the electrons (charge) have been injected into the floating gate 102, the first NMOS transistor 103 is not turned ON, even if the high-level control gate control signal cg is applied, because the voltage actually applied to the floating gate 102 is at a low level. Therefore, the voltage of the input node bit of the inverter pair 105 is a high level voltage of about 1 V, thereby representing logic 1.
On the other hand, if no electrons have been injected into the floating gate 102, the application of the high-level control gate control signal cg to the control gate causes capacitive coupling between the gate capacitance of the PMOS transistor 101 and that of the first NMOS transistor 103, such that the voltage of the floating gate 102 is increased to turn ON the first NMOS transistor 103. As a result, the voltage of the input node bit of the inverter pair 105 is a low level voltage of about 0 V, thereby representing logic 0.
Since the data write operation and the data read operation are performed in this manner, the electrons injected into the floating gate 102 remain confined in the floating gate 102 even if the device is turned off. Therefore, when the power is turned on again to perform a read operation, the state of the data written based on whether or not the electrons have been injected into the floating gate 102 is determined to read the data.
However, due to the fact that the thickness of gate oxide films has been reduced as a result of the recent advancement of miniaturization, leakage of the electrons injected into the floating gate 102 has become noticeable. This causes a first problem in that the data retention characteristics of the downsized MOS transistor 103 deteriorate.
In a so-called system LSI in which a logic section and a memory section are formed on the single chip, the gate oxide film thickness of typical MOS transistors is about 2 nm, while the gate oxide film thickness of transistors in I/O circuits serving as peripheral circuits is about 7 nm in the process generation in which, e.g., the design rule is 130 nm. In such gate oxide films whose thickness is not greater than 10 nm, leakage caused by their own defects and leakage due to tunnel current increase.
Furthermore, nonvolatile memories are used not only for forming memory arrays for storing large amounts of user data, but also as peripheral circuits of system LSIs for storing system information such as the presence/absence of redundancy repair and system configuration selection, as described in the above patent publication. These peripheral circuits are often disposed near a power source on the chip, which produces a second problem in that noise generated by variation in the power source potential enters the nonvolatile memories, such that their operation is likely to become unstable.